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[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[Other resource] VHDL.fifo

Description: 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
Platform: | Size: 1178849 | Author: 黎莉 | Hits:

[Other resource] fifo_vhd_131

Description: fifo vhdl源程序-fifo vhdl source
Platform: | Size: 15492 | Author: zlw | Hits:

[Other resource] FIFO

Description: VHDL源代码程序，使用VHDL语言编写，一个FIFO的代码实现工程
Platform: | Size: 3751 | Author: 罗兰 | Hits:

[Other resource] FIFO

Description: FIFO的源代码，对FIFO设计有帮助，有借鉴意义，帮助学习VHDL编程
Platform: | Size: 908 | Author: 胡清泉 | Hits:

[Other resource] fifo-1117

Description: 这是异步FIFO的VHDL实现代码，已经在FPGA上通过实践证明，运行状态良好
Platform: | Size: 20434 | Author: 杨宇 | Hits:

[Other resource] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家
Platform: | Size: 1678507 | Author: SL | Hits:

[Other resource] fifo8x9

Description: 8位深，9位宽FIFO VHDL源码设计，如需改进可在此基础上扩展
Platform: | Size: 1077 | Author: lxy | Hits:

[Other resource] fifo

Description: 使用VHDL编程的异步FIFO程序 经调试可运行
Platform: | Size: 131086 | Author: 张星 | Hits:

[Other resource] VHDL

Description: 高质量的VHDL代码乒乓处理FIFO缓存
Platform: | Size: 915 | Author: wode | Hits:

[Other resource] FIFO

Description: 用VHDL语言编写的实现FIFO的设计，经编译下载成功
Platform: | Size: 67226 | Author: henry | Hits:

[Other resource] RS232uart(VHDL)

Description: 256字节深度的RS232串口程序,共分4个模块,顶层文件\\FIFO程序\\串口收和串口发.经过测试已用于产品.可靠!
Platform: | Size: 5377 | Author: 温海龙 | Hits:

[Windows Develop] fifo源程序

Description: fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
Platform: | Size: 1136 | Author: 许 | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

[Embeded-SCM Develop] fifo

Description: FIFO的VHDL代码，最简单的同步FIFO设计，仅供参考-FIFO VHDL code
Platform: | Size: 403456 | Author: justin | Hits:

[VHDL-FPGA-Verilog] FPGA-FIFO-VHDL

Description: 这是一个基于FPGA的异步FIFO设计，利用的VHDL硬件描述语言，内容分析清楚，附带完整代码-This is an FPGA-based asynchronous FIFO design, the use of VHDL hardware description language, content analysis, with complete code
Platform: | Size: 74752 | Author: yanjiajun | Hits:

[assembly language] fifo

Description: 同步fifo vhdl语言 16乘以8 能够进行仿真- 16 synchronous fifo vhdl language can be simulated by 8
Platform: | Size: 18432 | Author: 浅桑 | Hits:

[MPI] FIFO

Description: FIFO读写操作，quartusII VHDL IP FPGA-FIFO VHDL IP FPGA
Platform: | Size: 100352 | Author: eclipseds5 | Hits:

[VHDL-FPGA-Verilog] CCD_Array

Description: Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
Platform: | Size: 3320832 | Author: muralidh | Hits:

[VHDL-FPGA-Verilog] fifo-vhdl

Description: code fifo by spartan6
Platform: | Size: 14513 | Author: dornabit | Hits:
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